Radio Frequency (RF) clock dividers are well known and commonly used in communication systems. The clock divider is an important building block in many RF circuits, such as the phase-locked loop (PLL) circuit. In a typical PLL, the output of a voltage-controlled oscillator (VCO) is divided down by a clock divider to a frequency output by a temperature-compensated crystal oscillator (TCXO) (e.g., typically from 10 MHz to 30 MHz). The divided signal and TCXO frequencies are compared in a phase/frequency detector, and the output difference signal is filtered and used to adjust the VCO output frequency.
Another important application of a clock divider is to generate related clock signals having certain phase relationships. Most modern wireless communication systems employ modulation schemes utilizing complex values, with modulated symbols occupying both In-phase (I) and Quadrature (Q) vector space, where the I and Q axes represent a phase shift of 90 degrees. Frequency downconverting mixers and demodulators are thus commonly implemented with separate I and Q signal paths. Hence, a clock divider that not only frequency-divides a periodic signal from a source (e.g., a crystal oscillator or VCO), but also supplies the divided clock in two outputs, one phase-shifted by 90 degrees from the other, is particularly advantageous. Compared with analog resistor and capacitor (RC) quadrature generation techniques, the multi-phase frequency divider approach is easier to implement, consumes lower power, and offers smaller phase imbalance.
FIG. 1 depicts a conventional, latch-ring implementation of a balanced, quadrature-phase, divide-by-two clock divider circuit. This architecture is based on two D-latches connected in series, and clocked by alternate phases of a differential clock signals. “Cp” is a positive clock signal clocking the first D-latch. “Cn” is a balance, negative clock signal—180 degrees out of phase with Cp—clocking the second D-latch. The input of the first latch is the inverted output of the second latch. The outputs AA and CC comprise one balanced clock output having half the frequency of Cp/Cn. The outputs BB and DD comprise a second balanced clock output, also having half the frequency of Cp/Cn, and being 90 degrees out of phase with AA/CC.
Conventional RF clock divider circuits often exhibit numerous deficiencies. They have a limited maximum operating frequency, and/or high current consumption. They may lack a full swing output signal swing (rail-to-rail). Some designs are not balanced, or not fully differential. Some designs impose a high capacitive load in the driving circuit, (e.g., a VCO). In addition, some divider topologies have limited sensitivity when the input signal is small.